- Applicable Business Areas
- Automotive parts, Semiconductor
- Target Applications
- Power semiconductors for automotive devices
Die-bonding materials which are used directly under heat generating semiconductor chips need to quickly dissipate heat to radiating parts such as thermal interface materials (TIMs) or heat sinks for ensuring semiconductor chip performance.
Although high-lead solder is widely used in die-bonding applications for semiconductor chips its thermal conductivity is limited to around 30 W/(m・K) and the amount of thermal conduction is insufficient. Therefore a sintered silver paste with high thermal conductivity has been introduced as a substitute. However it requires high pressure when used in the die-bonding process which raises problems such as the breaking of semiconductor chips during processing. For this reason, we have developed “sintered copper die-bonding paste,” which has higher thermal conductivity (180 W/(m・K)) than high-lead solder and allows a die-bonding without thermal compression pressure or with low thermal compression pressure.
High thermal conductivity (180 W/(m・K)) can resolve problems relating from to high-lead soldering
Conventionally high-lead solder is widely used in power semiconductors due to its high connection reliability among solder materials. However its thermal conductivity is lower than those of other component materials resulting in a challenging bottleneck issue during heat dissipation. In contrast to a general high-lead solder with 30 W/(m・K) of thermal conductivity our sintered copper die-bonding paste has an increased thermal conductivity (180 W/(m・K)) to be used as an ideal die-bonding material to overcome the temperature increase in power semiconductors.
Temperature distribution on sample cross-sections
(a) Sample with sintered copper die-bonding paste
Heat is dissipated from the chip to the board - keeping the chip temperature low.
(b) Sample with high-lead solder
Heat cannot be dissipated - increasing the chip temperature.
(Items set other than material properties)
Electrical power, environment temperature: measured values of samples, air properties: air at normal pressure and 30℃ (other physical quantities: fixed values), density: 1.161 kg/m3, thermal conductivity: 2.610 x 10-2 W/(m∙K), coefficient of molecular viscosity: 1.840 x 10-5 N∙s/m2, thermal expansion coefficient: 3.333 x 10-3K-1, conduction, radiation, heat transfer by natural convection, buoyancy, and turbulence were taken into account.
Maintains high connection reliability even when the operating temperature is >175℃
Die-bonding with high-lead solder has the problem that the die-bonding layer suffers fatigue fractures due to the stress caused by the difference in the thermal expansion of parts resulting in the connection of semiconductor chips not being operating adequately. During the power cycle test (Tj,max = 175 ℃) it has been proved that our sintered copper die-bonding paste ensures a higher number of cycles than high-lead solder and sintered silver, has good durability and can maintain the connection reliability of semiconductor chips.
Power Cycle Test Weibull Analysis Results (Tj,max = 175 ℃)
High thermal conductivity (180 W/( m∙K))
The product has a high thermal conductivity (180 W/(m∙K)) which is five or more times that of high-lead solder (30 W/(m∙K)) and is most suitable as a die-bonding material for semiconductor chips that are subject to the highest thermal load among power semiconductors.
Two types are available: non-pressure or pressure bonding type
Our lineup of sintered copper die-bonding paste consists of two types: a “non-pressure bonding type” that does not require thermal compression pressure (required gas atmosphere: hydrogen) and a “pressure bonding type” that allows for bonding with 2 MPa or less of thermal compression pressure. Compared to sintered silver paste which is a die-bonding material also having high thermal conductivity and a thermal compression pressure of 20 MPa our product allows for bonding with one-tenth of that pressure. Therefore a contribution to the improvement in the yield rate during semiconductor chip mounting is expected.